1. Field of the Invention
The present invention relates to a display panel, and especially to the pixel layout of a pixel array and a display panel applying the same.
2. Description of Related Art
FIG. 1 is a schematic diagram of a conventional liquid crystal display. The liquid crystal display 100 includes a display panel 101 having a delta type pixel array, a plurality of data lines DL, and a plurality of scan lines GL disposed thereon. Referring to FIG. 1, the sub-pixels of the first and the last sub-pixel rows are not disposed on the same shaft. Hence, the wire arrangement of the data lines in the display panel 101 is in a step-type arrangement. Each of the data lines DL in the display panel 101 is correspondingly coupled to one of source lines of a source driver 103.
The sub-pixels disposed on the same shaft in the delta type pixel (such as the sub-pixels SP1 and SP2 shown in FIG. 1) are electrically connected to different data lines DL. Therefore, the wire lengths of the data lines DL corresponding to the sub-pixel SP3 in the second sub-pixel row and the sub-pixel SP4 in the last sub-pixel row within an area A have to be increased, in order to electrically connect the corresponding source line of the source driver 103. The wire lengths between the delta type pixel array and the data lines DL in the display panel 101 are thus different. As a result, the wire impedance of each of the data lines DL is different and the frame resolution of the display 100 is uneven.
It is noted that the wire lengths of the data lines DL corresponding to the sub-pixel SP3 in the second sub-pixel row and the sub-pixel SP4 in the last sub-pixel row on the left side of the display panel 101 have to be increased to connect with the corresponding source lines of the source driver 103, and thus the space for the wire arrangement around the delta type pixel array in the display panel 101 is enlarged. Due to the complexity of the wire arrangement between the delta type pixel array and the data lines DL in the display panel 101 is increased, so the manufacture process will be difficult and decreased production yield.
Furthermore, the sub-pixels on the same row in the delta type pixel array of the display panel 101 are electrically connected to different data lines DL in the display panel 101. Hence, the number of the source lines of the source driver 103 has to be increased, such that the number of the source lines of the source driver 103 is the same as the number of the data lines DL in the display panel 101. However, since as many source lines of the drivers 103 as the data lines DL are used in the display panel 101, additional production costs are introduced.
It is further noted that in the delta type pixel array of the conventional display panel 101, each sub-pixel row has to be electrically connected with one scan line GL to receive a scan voltage (Vscan) outputted by a gate driver 105, in order to enable the thin film transistors (TFTs) in the sub-pixel row. In addition, in order to increase the charge efficiency of the TFT of each sub-pixel in each sub-pixel row, the size of the TFT is increased, while the aperture ratio of the sub-pixel is reduced and the transmittance of the display panel 101 is decreased accordingly.